"Pipelining", in the context of a processor, means that the CPU scheduler creates a specific list of linked instructions (actions) to be fed to the computation units to work. Generally speaking, this list is a series of actions which require the successful completion of the prior one - so, action A completes, then action B takes the output from A and does something, while action C then does something with the output of B, etc.
Pipelining can bring significant performance benefits, as each successive action finds all its prerequisites already satisfied, so the action is ready to go immediately.
The pipeline is filled by the CPU scheduler from a pool of work which is waiting to occur. Each execution unit has a pipeline associated with it, so as to have work pre-planned.
In a non-pipelined CPU, the scheduler merely chooses from the pool of waiting work each time an execution unit signals it is free.
Pipelined CPUs are significantly more efficient than non-pipelined CPUs, provided the scheduler can keep the pipeline full. If work on an execution unit produces an output that the scheduler had not predicted (i.e. a jump rather than a computation output), then the pipeline stalls, and it has to be completely emptied, while the scheduler reorders work to account for the new outcome.
Thus, the efficiency of a pipelined CPU is entirely dependent on the CPU scheduler's effectiveness at predicting the outcome of each instruction (action). If the workload is such that the predictive scheduler can't do a good job, and frequent pipeline stalls occur, then it will often be the case that a non-pipelined design will perform better on that workload.
The tradeoff is thus: the longer the instruction pipeline for an execution unit, the better performance that unit can have, but the harder (and more complex) the work is for the predictive scheduler, and the greater the cost (in terms of performance hit) that a pipeline stall is.
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