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It depends what ARM you're talking about. The ARM7 uses the Van Neumann bus architecture (one bus for both data and instructions, and never both at the same time). The ARM9 uses a Harvard bus architecture (separate buses, one each for data and instructions).
The main limitation of the von Neumann architecture is known as the "von Neumann bottleneck". This is due to the fact that all instructions and all data must pass through the same shared common multiplexed bus to get in or out of the processor, sooner or later things have to wait for other things to get access to this multiplexed bus and the processor gets starved for instructions and/or data. The result is the processor is unable to maintain its designed performance but waits idle instead of doing work. There is no complete solution to the "von Neumann bottleneck" with the von Neumann architecture, but many things have been tried over the years. The most effective one so far has been the use of independent instruction and data L1 caches. This at least allows blocks of frequently needed instructions and data to be held in 2 separate very high speed memories and made available to the processor on 2 independent busses, so that instructions won't have to wait for data and data won't have to wait for instructions. But even with this, the bottleneck still occurs on the main bus when less frequently needed instructions and/or data must be accessed.
Rivals? IBM had an architecture that Apple wanted for Mac, the POWER, and Motorola had their 88000 microprocessor memory bus interface. They combined these to define the PowerPC subset architecture specification of the POWER architecture specification. IBM also wanted to build less expensive POWER workstations and needed help converting the POWER implementation, which was often a multi-card CPU to a single chip microprocessor to do so.
The name of the bus boycott was the Montgomery Bus Boycott.
because she sat in the bus but did not to leave