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1. Syncrhonous bus includes clock in control lines whereas asynchronous bus is not clocked.

2. the devices which need to be connected by synchronous bus should be at same speed whereas an asynchronous bus may connect many devices with varying speeds.

3. A fixed protocol is defined to communicate using synchronous bus which is relative to the clock. An asynchronous bus uses handshaking protocol.

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A synchronous logic all will happen synchronized with a clock timing. For an asynchronous logic states will changes irregardless of clock timing.

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Q: Difference between synchronous bus and asynchronous bus?
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asynchronous bus A bus that interconnects devices of a computer system where information transfers between devices are self-timed rather than controlled by a synchronizing clock signal.

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Conventional DRAM, of the type that has been used in PCs since the original IBM PC days, is said to be asynchronous. This refers to the fact that the memory is not synchronized to the system clock. A memory access is begun, and a certain period of time later the memory value appears on the bus. The signals are not coordinated with the system clock at all, as described in the section discussing memory access. Asynchronous memory works fine in lower-speed memory bus systems but is not nearly as suitable for use in high-speed (>66 MHz) memory systems. A newer type of DRAM, called "synchronous DRAM" or "SDRAM", is synchronized to the system clock; all signals are tied to the clock so timing is much tighter and better controlled. This type of memory is much faster than asynchronous DRAM and can be used to improve the performance of the system. It is more suitable to the higher-speed memory systems of the newest PCs.

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