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TaigaPolling interrupt (CPU keeps polling at regular intervals if a device is ready)
vectored interrupt (I/O device requests for attention)
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A CPU generally handles an interrupt by executing an interrupt service routine?
By checking the interrupt register at fixed time intervals
What is an interrupt How are multiple interrupts dealt with?
An interrupt is a request to execute different code, initiated usually by a hardware condition such as data-ready or operation-complete, but also sometimes initiated by the running program. The processor saves its immediate state, IP and Flags, on the stack and loads a new IP value, effectively doing a CALL sequence to some interrupt service routine. The routine does whatever processing is required, and returns, restoring the running program. Under normal conditions, the interrupt response sequence disables further interrupts, so that recursive entry does not occur. The service routine reenables interrupts just before returning, so that pending or further interrupts can be processed. If multiple interrupt levels are to be supported, such as in the 8085, the interrupt service routine can set the interrupt mask, blocking the level in progress, and then reenable interrupts. This way, a second interrupt on a higher level can be processed while the first interrupt is being processed. On return, the lower level interrupt disables interrupts, restores the mask, and then reenables interrupts prior to return.
What is a TrapHandler?
A trap handler, also called an interrupt handler or interrupt service routine (ISR) is a program that executes when predefined events occur in a computer. There are software and hardware interrupts. An interrupt causes the computer's processor to stop running its current task and immediately run the trap handler to service the interrupt.
What is HISR and LISR in embedded systems context?
HISR: High Level ISR (Interrupt Service Routine) LISR: Low Level ISR
Should any device be allowed to interrupt CPU while another interrupts are being serviced?
It is possible to allow nested interrupts. This is often done when there is a heirarchy of interrupts, some with higher priority than others. In order for this to work, the second interrupt must not be allowed to influence the progress of the first interrupt. We call this being "thread safe". In a nested scheme, an interrupt mask is set so that higher priority interrupts can be permitted, while blocking interrupts of the same or lower priority, and then interrupts are reenabled during the interrupt service routine. At the conclusion of the first routine, interrupts are disabled again, the mask is restored, and the normal interrupt return sequence is executed. In the 8085, this can be supported using the Read Interrupt Mask (RIM) and Set Interrupt Mask (SIM) instructions. While not strictly required, the logical priority is often INTR, RST5.5, RST6.6, RST7.5, and then TRAP, in order of increasing priority.
