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What is program code?
They are basically words or simbles written out to make a program. Here is a simple one if you want to make one open a website 1 open notepad by doing Start>all programs>accessories>notepad 2 paste this in @echo off cls title Website opener color 4b Set /p website= Type The website you would like to goto echo Opening %website% start www.%website%.com exit 3 goto file save as whatever.bat 4 bellow that select All files instead of txt document. 5 open and enjoy You will need an internet connection
How Product life cycle of ballpoint pen?
The life cycle of a ballpoint pen is: 1.The pen is produced. 2.Somebody buy's the pen 3.Here the pen's life can differ, the pen can; 3a.Be taken to a school and be kept in a pencilcase. 3b.Be taken to a private/public building e.g work, home. 4a.At a school the pencil will be lost or stolen or taken home and lost there in which case refer to 4b. 4b.At a private/public building the pen will be; lost in which case the loser will get another; destroyed either during demolition of the building or too much force exerted on it e.g squeezed, stood on. Or it dry's up. 5a.The person who stole the pen or the person who finds the pen will in turn loose it or have it stolen. 5b.If at a public building the pen is refound it will be reused until it is lost again. The pen's life will evenetually end in its destruction or the latter option in 4b, there is a tiny percentage of pens however that are used up, this happens about thrice in every users lifetime. 6a.If still at school the pen has as a high chance of breaking bu some are lost or dry up. N.B.In my own time at school i have never used a pen so much it has run out of ink and my time at shool is almost over. Though i only use biro's which contain alot of ink, unlike some of the cheaper pens i have seen which only contain a flat ink cartidge the shape of the pen is misleading, it makes the cartidge look round when in actual fact it is not. chuck Norris can sneeze with his eyes open
What is the process for designing VLSI and ASIC chips?
Step 1: Prepare an Requirement Specification Step 2: Create an Micro-Architecture Document. Step 3: RTL Design & Development of IP's Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly. Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL Step 4b: Perform Property Checking , to verify the RTL implementation and the specification understanding is matching. Step 5: Prepare the Design Constraints file (clock definitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an SDC file(Synopsys constraint file, specific to synopsys synthesis Tool (design-compiler) Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which synthesis needs to be targeted for, which has the functional/timing information available for the standard-cell library and the wire-load models for the wires based on the fanout length of the connectivity), RTL files and the Design Constraint files, So that the Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet the design-constraints requirements. After performing synthesis, as a part of the synthesis flow, need to build scan-chain connectivity based on the DFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds the scan-chain. 7: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT) after synthesis. Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting the power targets. Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the functional requirements. Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that the synthesis Tool has not altered the functionality. Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format) file and synthesized netlist file, to check whether the Design is meeting the timing-requirements. Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement. Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog format) and the SDC (constraints file) is passed as input files to the Placement and Routing Tool to perform the back-end Actitivities. Step 9: The next step is the Floor-planning, which means placing the IP's based on the connectivity,placing the memories, Create the Pad-ring, placing the Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements(Simultaneous Switching Noise) that when the high-speed bus is switching that it doesn't create any noise related acitivities, creating an optimised floorplan, where the design meets the utilization targets of the chip. Step 9a : Release the floor-planned information to the package team, to perform the package feasibility analysis for the pad-ring . Step 9b: To the placement tool, rows are cut, blockages are created where the tool is prevented from placing the cells, then the physical placement of the cells is performed based on the timing/area requirements.The power-grid is built to meet the power-target's of the Chip . Step 10: The next step is to perform the Routing., at first the Global routing and Detailed routing, meeting the DRC(Design Rule Check) requirement as per the fabrication requirement. Step 11: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is generated. Step 12: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and Routing step. Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design has met the power targets. Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the design is meeting the functional requirement . Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that the place & route Tool has not altered the functionality. Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file, to check whether the Design is meeting the timing-requirements. Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement, Peform the Fault-coverage with the DFT tool and Generate the ATPG test-vectors. Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL) Step 12g: Perform DRC(Design Rule Check) verfication called as Physical-verification, to confirm that the design is meeting the Fabrication requirements. Step 12h: Perform LVS(layout vs Spice) check, a part of the verification which takes a routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two are matching. Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is meeting the ERC requirement. Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and proper guarding is there in case if we have both analog and digital portions in our Chip. We have separate Power and Grounds for both Digital and Analog Portions, to reduce the Substrate-noise. Step 12k: Perform separate STA(Static Timing Analysis) , to verify that the Signal-integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF file(parasitics including coupling capacitances values), are fed to the tool. This check is important as the signal-integrity effect can cause cross-talk delay and cross-talk noise effects, and hinder in the functionality/timing aspects of the design. Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand the static and dynamic power-drops with in the design and the IR-drop is with-in the target limits. Step 13: Once the routed design is verified for the design constraints, then now the next step is chip-finishing activities (like metal-slotting, placing de-coupling caps). Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which the fab can understand, GDS file. Step 15: After the GDS file is released , perform the LAPO check so that the database released to the fab is correct. Step 16: Perform the Package wire-bonding, which connects the chip to the Package.
How do you Convert the hexadecimal number A5 to a decimal number?
D: 0-15 X: 0-F Dec Hex 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 A 11 B 12 C 13 D 14 E 15 F D:16-31 X: 10-1F Dec Hex 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 26 1A 27 1B 28 1C 29 1D 30 1E 31 1F D: 32-47 X: 20-2F Dec Hex 32 20 33 21 34 22 35 23 36 24 37 25 38 26 39 27 40 28 41 29 42 2A 43 2B 44 2C 45 2D 46 2E 47 2F D: 48-63 X: 30-3F DecHex 48 30 49 31 50 32 51 33 52 34 53 35 54 36 55 37 56 38 57 39 58 3A 59 3B 60 3C 61 3D 62 3E 63 3F D: 64-79 X:40-4F Dec Hex 64 40 65 41 66 42 67 43 68 44 69 45 70 46 71 47 72 48 73 49 74 4A 75 4B 76 4C 77 4D 78 4E 79 4F D:80-95 X: 50-5F Dec Hex 80 50 81 51 82 52 83 53 84 54 85 55 86 56 87 57 88 58 89 59 90 5A 91 5B 92 5C 93 5D 94 5E 95 5F D: 96-111 X: 60-6F Dec Hex 96 60 97 61 98 62 99 63 100 64 101 65 102 66 103 67 104 68 105 69 106 6A 107 6B 108 6C 109 6D 110 6E 111 6F D: 112-127 X:70-7F Dec Hex 112 70 113 71 114 72 115 73 116 74 117 75 118 76 119 77 120 78 121 79 122 7A 123 7B 124 7C 125 7D 126 7E 127 7F D: 128-143 X: 80-8F Dec Hex 128 80 129 81 130 82 131 83 132 84 133 85 134 86 135 87 136 88 137 89 138 8A 139 8B 140 8C 141 8D 142 8E 143 8F D: 144-159 X: 90-9F Dec Hex 144 90 145 91 146 92 147 93 148 94 149 95 150 96 151 97 152 98 153 99 154 9A 155 9B 156 9C 157 9D 158 9E 159 9F D: 160-175 X: A0-AF DecHex 160 A0 161 A1 162 A2 163 A3 164 A4 165 A5 166 A6 167 A7 168 A8 169 A9 170 AA 171 AB 172 AC 173 AD 174 AE 175 AF D:176-191 X: B0-BF Dec Hex 176 B0 177 B1 178 B2 179 B3 180 B4 181 B5 182 B6 183 B7 184 B8 185 B9 186 BA 187 BB 188 BC 189 BD 190 BE 191 BF D: 192-207 X: C0-CF Dec Hex 192 C0 193 C1 194 C2 195 C3 196 C4 197 C5 198 C6 199 C7 200 C8 201 C9 202 CA 203 CB 204 CC 205 CD 206 CE 207 CF D: 208-223 X: D0-DF Dec Hex 208 D0 209 D1 210 D2 211 D3 212 D4 213 D5 214 D6 215 D7 216 D8 217 D9 218 DA 219 DB 220 DC 221 DD 222 DE 223 DF D: 224-239 X:E0-EF Dec Hex 224 E0 225 E1 226 E2 227 E3 228 E4 229 E5 230 E6 231 E7 232 E8 233 E9 234 EA 235 EB 236 EC 237 ED 238 EE 239 EF D: 240-255 X: F0-FF Dec Hex 240 F0 241 F1 242 F2 243 F3 244 F4 245 F5 246 F6 247 F7 248 F8 249 F9 250 FA 251 FB 252 FC 253 FD 254 FE 255 FF
What is a reentry code RE-4B in the military?
RE-4B is an Air Force reenlistment code, given to indicate a discharge for exceeding body fat standards.
What is 3a plus 4b - 5 - a?
2a + 4b - 52a + 4b - 52a + 4b - 52a + 4b - 5
What is RE-4B in US Marine Corps?
It is a Military RE-Code or Re-Enlistment code. An RE-4B means that a person is not eligible for reenlistment in the US Marine Corps due to drug use. It is generally associated with a dishonorable discharge!
What is NEC 210-4B?
It is a electrical code rule taken from the National Electrical Code book. It has to do with multi wire branch circuits.
What is 8b minus 4b?
8b - 4b = 4b
What is 5b equals 21 plus 4b?
5b = 21 + 4b 5b - 4b = 21 + 4b - 4b b = 21
SOLVE 4b-1 equals -4 plus 4b plus 3?
4b - 1 = -4 + 4b + 3first, simplify and add together what you can.4b - 1 = -1 + 4b4b = 4bbecause 4b is always equal to 4b, the answer is infinite.
4 x b-1 plus -4 plus 4b?
Well if it is worded right then 4xb-1+(-4)+4b=4b-1-4+4b=4b+4b-1-4=8b-5
What is 8b-4b?
12
Which expressions are equivalent to 4b?
4b-b
2a-4b plus 4b-6a equals a plus b?
2a-6a-a=b+4b-4b -5a=5b-4b -5a=1b a=-5 b=1
Whats -4b plus 2 equals 18?
-4b+2 = 18 -4b = 18-2 -4b = 16 b = -4
