What is the limitations of jk flip flop?

Answer 1

When j=1 an k=1 and the clock pulse signal which remain at logic 1, after the output have been complemented once will cause repeated and continue transmission of output. This situation is called "raised condition".

To avoid this undesirable operation, the clock pulse must have a time duration which is shorter then the propagation delay through the flip flop.

Answer 2

W