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Debouncing is a provision in electronic/electrical devices having switches to prevent the spikes in output.
Details: When we press any switch manually and release it it bounces due to inherent elasticity, this causes multiple make and break of electrical contact. If the response time is very large then it won't create any problem, but if it is small then we get multiple responses for a single keypress.
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What is key debouncing in 8051?
wnenever a mechanical puch button is pressed or released once, the mechanical components of the key not changed the position smootly, it take some time to released it.this is c/as kydeboucning.
Draw Circuit for keyboard interfacing with 8086?
For interfacing to the microprocessor system, usually push buttons keys are used. Whenever a key is pressed, there are small mechanical vibrations that cause noise on the input, which can cause the microprocessor to detect several keypresses instead of just one. Bouncing happens because of the tendency of any two metal contacts in an electronic device to generate multiple signals as the contacts close or open. You can solve this problem using software or hardware debouncing. The hardware approach is shown in figure 8.1. It uses a cross-coupled latch formed with two Nand gates Simple Keyboard Interface: The figure 8.3 shows the simple keyboard interface Manipal University Page No.: 195 When port pin is logic 1,key is open,otherwise key is closed. The software routine to get key code with key debounce is: In the technique shown in figure 8.3, each key requires separate interface.This means, to interface one key,one input line is required.This is the disdavantage as it requires many line as many keys. This number of lines required can be reduced if keys are put in matrix form. The figure 8.4 shows the interface of matrix key board The 16 keys are arranged in four rows and four columns. The connection will be made such that when a key is pressed, it shotrs the corresponding one row and one column. Two ports are required, input port for connecting rows and and output port for connecting columns. The lines connected to rows are called returned lines and the lines connected to columns are called scan lines When all a key is pressed it shorts the corresponding row and column. If the output line of this colummn is low, then it makes the corresponding row line low,other wise the status of row line will be high. The pressed key will be identified by the data sent on the oputput port and the input code received from the input port. Figure 8.6 shows the flow chart for interfacing of 8086 As shown in the figure 8.7, the interfacing is done using 8255 PPI. The 8086 is being used in maximum mode and port A of 8255 is used for columns and port B for rows. By making use of the lookup table stored in the memory, the 8086 microprocessor will determine the code of the depressed key, then it will initiate the action. The figure 8.8 shows the flow chart for keyboard interface............
What is the difference between the nand gate ic's 74ls00 and 74ls132?
The 74LS00 is a logic NAND gate with normal logic level inputs. This means that the inputs has a low range below 0.8V, unrecognised range and a high range above 2V. At any time a input signal crosses those levels, a change in state can be expected. Applicable to the LS family, they have a floating input that means it is uncertain the state of logic level if no input is connected. Therefore never assume that since the input is not connected that the circuit will assume a zero, it can be either zero or one. The 74LS132 is also a NAND gate logic function. But different to the Logic level input it uses what we call a Schmitt trigger input to improve noise immunity in a circuit. In simple terms; it's really nothing more than a comparator input. But the Schmitt trigger also have a hysteresis, which help to eliminate the affect what noise have on the circuit. On a more technical note Each circuit contains a 2-input Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The totem pole is basically a push-pull output stage constructed with two p-n-p transistors and a diode on the output. The comparator function would mean that there is a particular threshold level on the input and if the input voltage pass the particular level, the output or intermediate state of the function will change state. In the case of multiple logic inputs the change of input state does not necessarily mean a change in output state and therefore I will refer to an intermediate area inside the function related to the input state. The hysteresis create a high and low trigger points. This cause the input to at least pass the high trigger point of about 1.6V before the intermediate state will change or drop below the 0.9V before the intermediate state change back again. Therefore the practical unit will not have one particular level to change state but these two fixed trigger points must be used. It sounds like it complicates matters but it really helps to handle input noise signals which makes the Schmitt trigger a handy device. Making it a good device for signal conditioning of logic signals in some applications. Also take note that the high and low hysteresis trigger points may vary with supply voltage. In fact I do not recommend it as standard practice to use a Schmitt trigger to evaluate analogue levels, some engineers may differ but I would rather refer to a real comparator circuit design where you have more control over precision, trigger points and reference levels. But may be considered for logic inputs from sensors or conditioning of logic signals Some circuits may also employ Schmitt trigger devices for oscillators and contact debouncing
